1. Field of the Invention
The present invention relates in general to floating gate non-volatile memories, and more specifically to slew rate control of a charge pump that develops a voltage used for erasing and programming of floating gate non-volatile memories.
2. Description of the Related Art
Floating gate non-volatile memories such as erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), block erasable (“flash”) EEPROMs, and one time programmable read only memories (OTPROMs) are typically used for many electronic applications such as automotive control, consumer products, etc. The state of each memory cell of a floating gate memory block is determined by the amount of charge stored on a floating gate. The floating gate is isolated from an underlying channel by a region of tunnel oxide. Typically, the floating gate transistor is programmed and erased by processes known as hot carrier injection and Fowler-Nordheim tunneling, respectively. One process that uses Fowler-Nordheim tunneling for erasing a flash memory is called “channel erase”.
A typical flash memory cell manufactured using a “triple well” process may have five terminals that must be properly biased for program and erase operations: a control gate, a source, a drain, a P-well terminal, and a deep N-well terminal. An array of flash memory cells is formed in the P-well. The P-well is isolated within the deep N-well. One technique for performing a channel erase operation on, the memory cells of the flash memory array involves applying a relatively high negative voltage, for example about −9 volts, to the control gate, while applying a relatively high positive voltage, for example about +9 volts, to the P-well and the deep N-well.
A typical memory device integrated onto a chip (e.g., integrated circuit or “IC”) includes multiple blocks of memory arrays of various sizes, such as, for example, one or more of each of a 16 kilobyte (KB) block, a 64 KB block, a 128 KB block, etc. A charge pump or the like is often used to drive the erasure voltage to each cell of one or more selected memory blocks on the IC to perform an erase operation. The output of the charge pump ramps to the selected voltage level at a slew rate based on a given clock frequency and as regulated by a feedback loop including a comparator or the like. As understood by those skilled in the art, each memory cell presents a capacitance to the output of the charge pump, and the combined capacitive load depends on which of the memory blocks are selected for the erase operation. A smaller memory block presents less capacitive load than a larger memory block even though the same charge pump circuit is typically used to erase either one at different times (or both at the same time). Since the output of the charge pump ramps from an initial voltage level (e.g., 0 V) to the same target voltage based on a given clock frequency, it takes longer for the charge pump circuit to achieve the target voltage level for the larger blocks. For example, a 128 KB memory block presents 8 times the capacitive load as a 16 KB memory block, so that it takes longer for the charge pump to achieve the target voltage for the 128 KB memory block.
The frequency of the clock signal is selected based on the largest memory block to be erased on the chip to achieve a given performance level (e.g., performance based on the amount of total time to complete the erase operation). Also, the response time of the comparator circuit used to control the charge pump regulated output is determined based on the allowable overshoot voltage for the largest memory block. Based on these conventional design constraints, the charge pump circuit is able to achieve the erase voltage significantly faster for the smaller memory blocks. It has been discovered, however, that if the voltage charges too quickly, then the charge pump output overshoots the target voltage by a substantial amount. The erase voltage of the typical memory cell is relatively close to its breakdown voltage, such as within 5%, so that an overshoot of more than 5% cannot be tolerated as it destroys the memory cells within the block.
It is possible to use a more sophisticated control circuit and/or a more complicated comparator circuit to avoid catastrophic failure of the memory device during the erase operation. Yet this first solution overly complicates the charge pump circuit and significantly increases the expense of the IC. Alternatively, it is possible to add a very large stability capacitor to the charge pump circuit. The additional stability capacitor also adds undue expense, consumes valuable space in the memory design, and negatively impacts desired performance levels.
It is desired to provide a charge pump circuit which achieves the target erase voltage for any and all selected memory blocks using a relatively simple and slow response comparator circuit without risking catastrophic failure of the of the chip.